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Counterpoint Research reports that YMTC is developing a DRAM prototype using a vertical-channel transistor 4F² cell design, with a targeted transfer rate of 9600 MT/s and mass production planned at Fab 3. The report follows Micron’s public skepticism about the architecture’s ability to scale; YMTC’s prototype and production plans have not been independently confirmed here.

YMTC is developing a DRAM prototype built around a 4F² memory-cell design and targeting a transfer rate of 9600 MT/s, according to a Counterpoint Research report. The reported project puts the Chinese memory maker on a different path from Micron, whose executives have questioned whether 4F² can provide a viable route to continued scaling.

Counterpoint says YMTC is extending its Xtacking additive technology—already used in its NAND work—into DRAM. The report describes a 9600 MT/s version using a vertical-channel transistor (VCT) 4F² cell structure that is under development, with mass production planned at Fab 3. It does not provide a production start date or say that the prototype has reached commercial readiness.

The report also describes a separate YMTC development effort: a 16-gigabit LPDDR5 product rated at 7500 MT/s, under research, development and testing at Fab 2 since October 2025. Counterpoint puts that work at about 5,000 wafer sheets per month and says the high-k metal gate process had not yet been applied to it. Those details concern the LPDDR5 effort, not necessarily the 9600 MT/s prototype.

Micron, meanwhile, said during a technology webinar that it had studied 4F² for more than two decades but saw no viable scaling path. Scott DeBoer, Micron’s president and chief technology and product officer, described what he called fundamental problems with scaling and characterized the density advantage over conventional 6F² cells as “somewhat akin to a myth.” That is Micron’s assessment, not a finding that YMTC’s design has failed.

A Different Route to DRAM Density

The disagreement matters because memory-cell layout affects how much DRAM capacity can be packed onto a chip as manufacturers push toward denser products. A 4F² design arranges a cell’s transistor and capacitor vertically, aiming to reduce the area each cell occupies compared with the conventional 6F² arrangement. If that approach can be manufactured reliably at scale, it could give a maker another way to improve density.

Wccftech’s report describes projected area and density benefits often associated with the architecture—roughly 30% to 40% less cell area and 30% to 50% more density per integrated circuit. These are potential design advantages, not measured results for YMTC’s reported prototype. Micron’s comments underline the central question: whether any density gain can be sustained as manufacturing processes advance.

For readers following the memory market, the development is a sign of competing engineering strategies, not proof that one company has solved the scaling problem. YMTC’s reported plans are at the development stage, while Micron is pursuing other approaches, including 3D DRAM. Commercial performance, yields, cost and production volume would determine whether the prototype changes the competitive picture.

How 4F² Differs From 6F²

In the 4F² layout described in the report, a memory cell’s transistor and capacitor are stacked vertically rather than arranged horizontally. The “F” represents the minimum feature size in the design; the 4F² label describes a cell footprint equal to four times that feature size squared. Wordlines and bitlines connect and operate the cell’s transistors.

China’s DRAM makers face limits on access to advanced lithography equipment, including extreme ultraviolet (EUV) systems, according to Wccftech’s account. It says CXMT is also pursuing 4F² and plans to introduce a DDR5 registered DIMM product based on the architecture before the end of 2026. Semiconductor expert Fred Chen was cited as saying a successful solution to the technology’s bottlenecks could let CXMT move its effective DRAM process from the 1c node to 1d. That outcome remains conditional.

Both CXMT and YMTC are also exploring high-k metal gate (HKMG) technology, which uses a high-dielectric-constant material in place of a conventional silicon-based gate insulator. The reported YMTC LPDDR5 project had not yet adopted HKMG as of the details given by Counterpoint; the report does not establish whether HKMG is part of the 9600 MT/s prototype.

“There are fundamental problems with 4F² scaling.”

— Scott DeBoer, Micron president and chief technology and product officer

Prototype Status and Production Timing

The available details do not confirm that YMTC has completed or demonstrated the 9600 MT/s prototype. Counterpoint describes it as being developed and says mass production is planned at Fab 3, but gives no schedule, output target, yield information or evidence that the planned production has started.

It is also unclear how the 9600 MT/s design would perform in power use, reliability, cost and manufacturing yield, or whether its stated transfer rate has been verified in a finished product. The reported 5,000-sheet monthly capacity applies to the separate LPDDR5 research and testing effort at Fab 2, not the planned Fab 3 production line. Micron’s broad criticism does not, by itself, establish the limits of YMTC’s specific implementation.

Evidence Needed From Fab 3

The next meaningful milestone would be confirmation that YMTC has produced and tested the VCT 4F² prototype, followed by details on its specifications and manufacturing progress. Any move from development to mass production at Fab 3 would clarify whether the company can turn the reported design into commercial DRAM.

Readers should also watch for updates on the distinct LPDDR5 project at Fab 2 and on CXMT’s stated DDR5 plans before the end of 2026. Until companies or research firms provide further verified results, the 9600 MT/s figure and Fab 3 production plan should be treated as reported development targets rather than demonstrated commercial outcomes.

Source: Wccftech

Key Questions

What is YMTC reportedly developing?

Counterpoint Research says YMTC is developing a DRAM prototype using a vertical-channel transistor 4F² cell structure, with a target transfer rate of 9600 MT/s.

Has YMTC started mass-producing the 9600 MT/s design?

The report says mass production is planned at Fab 3, but it does not say that production has begun or give a start date.

Why is Micron skeptical of 4F²?

Micron says it has studied the architecture for more than 20 years and sees no viable scaling path, citing fundamental scaling problems. This is Micron’s assessment; it does not independently establish the performance of YMTC’s design.

Is the 7500 MT/s LPDDR5 product the same as the 9600 MT/s prototype?

No. Counterpoint describes the 7500 MT/s 16-gigabit LPDDR5 effort as a separate project under development and testing at Fab 2. The 9600 MT/s VCT 4F² design is described as a follow-up project planned for Fab 3.

Source: Wccftech