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A China Times report cited by Wccftech says TSMC is discussing a CoWoS price increase of up to 20% amid strong demand for AI GPUs and custom ASICs. TSMC has not confirmed the reported increase; capacity expansion plans and longer equipment lead times are also described in the report.
TSMC may raise prices for its CoWoS advanced-packaging service by up to 20% as demand from AI GPU and custom ASIC makers puts pressure on production, according to a China Times report cited by Wccftech. TSMC has not confirmed the reported increase, and the available report does not identify a start date or say which customers would be affected.
The reported price adjustment is linked to sustained demand for packaging that combines multiple compute dies with high-bandwidth memory, or HBM, stacks. These larger and more complex packages can take longer to produce and test. The report says the added complexity reduces throughput, meaning manufacturers may need more equipment to maintain output even if the number of chips requested does not change.
Packaging and testing capacity are both under pressure, according to the report. It says equipment lead times have grown from three to six months to six to eight months as component suppliers also face capacity constraints. Those figures are reported industry conditions, not a separate public confirmation from TSMC.
The report describes TSMC as planning to increase CoWoS capacity to 130,000 wafers per month in 2026, with a target of 200,000 in 2027. It also says a U.S. plant is expected to begin production in 2028. The report does not specify the basis for those capacity figures or provide a detailed schedule for reaching them.
Semiconductor Supply · Reported Developments
AI Chip Demand Puts CoWoS Supply Under Pressure
A report says TSMC is discussing a CoWoS price increase of up to 20% as demand for AI GPUs and custom ASICs meets more complex packaging and longer equipment lead times. The proposed change remains unconfirmed.
Under discussion, according to the report
Reported, up from 3–6 months
Wafers per month, reported plan
Wafers per month, reported plan
More demand. Harder packages.
CoWoS brings compute dies and high-bandwidth memory (HBM) together in one package. Larger configurations add manufacturing and testing demands.
AI GPUs + custom ASICs
Strong demand for AI processors is competing for advanced packaging capacity, according to the cited report.
More dies, more HBM
Dense connections between multiple compute dies and HBM stacks create larger, more complex packages.
Longer build and test
Complex packages can take longer to produce and test, limiting output even if chip orders stay unchanged.
Demand meets a slow capacity ramp
The report describes pressure across both packaging and testing. New equipment and facilities take time to become usable production capacity.
More designs combine compute dies with HBM.
Production and testing can take longer.
Reported lead times extend to six to eight months.
Installation and validation delay usable output.
The report does not define the basis for these targets or provide interim milestones. It also says a U.S. plant is expected to begin production in 2028.
Alternatives depend on fit
Different approaches can suit different designs. The report describes technologies and development work, not confirmed customer moves away from CoWoS.
| Approach | What the report describes | Current status in account |
|---|---|---|
| TSMC CoWoS | Silicon interposer connects compute dies and HBM with dense connections. | Established ecosystem |
| Large CoWoS packages | 5× reticle-size packages in volume production; 9× and 14× versions in development. | Reported roadmap |
| CoPoS | Panel-based approach aimed at larger packages and lower costs. | Under development |
| Intel EMIB | Smaller silicon bridges embedded in an organic substrate; may suit some interconnect needs. | No confirmed customer switch |
Technology fit, production readiness, yields, memory arrangements, testing processes, and existing supply relationships all affect whether an alternative works for a given chip.
Cost, timing and flexibility
Any commercial or supply impact remains uncertain until TSMC confirms pricing and scope, and capacity plans become clearer.
“A new advanced packaging facility takes roughly three years to reach full load at its bottleneck stations.”
Wccftech, summarizing industry sources“TSMC says its 5× reticle-size packages are already in volume production with strong yields.”
Wccftech, reporting on TSMC’s packaging roadmapFour open questions
The next useful signals are direct pricing details and evidence that announced capacity is moving through installation and qualification.
Will TSMC confirm?
No. The up-to-20% figure is reported as under discussion. There is no confirmed effective date, final percentage, or customer list.
Which services are covered?
The report does not say whether the figure applies to all CoWoS services or specific package configurations.
Will the targets hold?
Track the reported 2026 and 2027 targets, plus the expected U.S. plant start in 2028. No interim milestones are provided.
Could designs move to EMIB?
EMIB may suit some designs, but the report identifies no confirmed switch. Technical needs and production readiness matter.
Would chip prices rise?
The report does not establish how any packaging price change would affect chip prices, customer budgets, or delivery times.
Higher Packaging Costs for AI Chips
If the reported increase is implemented, it could raise the cost of bringing advanced AI processors to market. CoWoS packaging is part of the manufacturing process for chips that place compute dies and HBM close together, so pricing changes may matter to GPU makers and companies developing custom AI accelerators. The scale of any effect on chip prices or customer budgets is not established by the report.
The report also points to a supply constraint that cannot be addressed immediately by announcing new factories. Advanced packaging lines require equipment installation, calibration and validation, and the account says new facilities can take roughly three years to reach full load at bottleneck stations. If demand remains strong while capacity ramps, customers may face both higher costs and longer waits. Those outcomes remain possibilities, not confirmed consequences of a price change.
For customers, packaging choices involve more than a quoted price. Switching technologies can require changes to chip design, memory arrangements and testing processes. A move to a competing option may offer a second source, but its suitability depends on the design and how quickly the alternative can meet production needs.
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Why CoWoS Is Under Pressure
CoWoS uses a silicon interposer to connect compute dies and HBM with dense connections. The Wccftech report says TSMC has 5x-reticle-size packages in volume production with strong yields, while 9x and 14x versions are in development. It also describes CoPoS, a panel-based packaging approach aimed at larger packages and lower costs, as a technology under development.
The report compares CoWoS with Intel’s EMIB, which uses smaller silicon bridges embedded in an organic substrate. It characterizes EMIB as suited to some moderate interconnect requirements and says supporters see its lower silicon use as an advantage and a possible alternative when CoWoS capacity is unavailable. That comparison is not a confirmation that customers are switching; the report says CoWoS benefits from an established ecosystem of design tools, memory partnerships and testing processes.
Capacity growth is a longer-running part of the issue. Building or expanding facilities can add production capability, but equipment availability and the qualification process affect when that capacity becomes usable. The reported increase in equipment lead times adds another constraint alongside the complexity and testing demands of larger AI packages.
“A new advanced packaging facility takes roughly three years to reach full load at its bottleneck stations.”
— Wccftech, summarizing industry sources
Price and Capacity Details Unconfirmed
TSMC has not confirmed the proposed price increase, and no effective date, customer list or final percentage has been provided in the report. It is also unclear whether the figure refers to all CoWoS services or only particular configurations, and whether customers would receive different terms.
The capacity figures and expansion timelines are reported plans, not independently detailed production forecasts in the account. The report does not state how many wafers are currently being processed each month, how the stated targets are defined, or how much output will be available to individual customers. It also does not establish how much of the pressure comes from AI GPUs, custom ASICs or other products.
The comparison with Intel EMIB is likewise not a direct measure of customer preference across the industry. Technical fit, production readiness, yields and existing supply arrangements can differ by chip design. No specific customer decision to change packaging providers is identified.
Confirmation and Expansion Milestones
The next key development would be direct confirmation from TSMC about whether it will change CoWoS pricing, along with any details on scope and timing. Until then, the reported 20% figure should be treated as a possibility under discussion rather than a finalized price change.
Capacity plans will also be worth tracking against the reported 2026 and 2027 targets, as well as the expected start of production at a U.S. facility in 2028. The account gives no interim milestones or production volumes for that plant. Equipment delivery, installation, calibration and qualification will affect how quickly announced capacity becomes usable.
Customers and the wider chip market may also watch for evidence that alternative packaging methods are being adopted for large AI designs. The report does not describe a confirmed shift away from CoWoS. For now, the clearest next steps are confirmation of pricing and updated details on capacity ramp-up.
Source: Wccftech
Key Questions
Has TSMC confirmed a 20% CoWoS price increase?
No. The figure comes from a China Times report cited by Wccftech. The report says an increase of up to 20% is being discussed, but TSMC has not confirmed it.
Why is CoWoS capacity strained?
The report links pressure to demand for AI chips that combine more compute dies and HBM stacks in a package. Larger, more complex packages can take longer to manufacture and test, limiting output.
When will TSMC add more CoWoS capacity?
The report gives targets of 130,000 wafers per month in 2026 and 200,000 in 2027, and says a U.S. plant is expected to begin production in 2028. TSMC has not confirmed these details in the account.
Could chip makers switch to Intel EMIB?
EMIB is described as a possible alternative for some designs, but the report identifies no confirmed customer switch. Design requirements, production readiness and existing manufacturing processes all affect whether a different packaging method is practical.
Source: Wccftech
